Aanchal Garg

Aanchal Garg

Aanchal Garg

Designation : Assistant Professor
Vidwan ID : 413459
Department : IT/CSE
Qualification : Ph.D (Pursuing), M.Tech, B.Tech
Experience : ~4 years of teaching experience in different universities.

Aanchal Garg is a faculty member and researcher specializing in nanoelectronics and semiconductor device engineering, currently associated with DBS Global University. Beyond research, she is deeply engaged in teaching core subjects such as digital electronics, operating systems, integrating innovative pedagogical approaches and AI-enabled learning strategies into her classrooms. She actively mentors undergraduate students in academic projects and technical skill development, fostering analytical thinking and practical exposure. Her academic vision combines research excellence, effective teaching methodologies, and continuous learning to contribute meaningfully to engineering education and technological advancement.

Research, Publications

  • Vertical Channel Dielectric Modulated Trench Dopingless Double Gate Junctionless FET Based Biosensor Deepti Gola; Sandeep Kumar; Aanchal Garg; Tripuresh Joshi; Balraj Singh ECS Journal of Solid State Science and Technology (2026)
  • Effect of drain region doping on performance of a vertical dual-gate JLFET Garg A.;Gola D.;Singh B.;Singh Y. Physica Scripta , Vol. 100 (2025) , pp.
  • Enhancing Effective Spectrum Utilization in 6G Cellular Networks via Sharing Algorithms kudari J.M.;Garg A.;Sridevi S.;Savita Lecture Notes in Electrical Engineering , Vol. 1274 LNEE (2025) , pp. 73-79
  • Developing Algorithms for Adaptive Network Coding and Its Impact on Wireless Network Performance Garg A.;Poornima S.;Savita ;Nachappa M.N. Lecture Notes in Electrical Engineering , Vol. 1274 LNEE (2025) , pp. 66-72
  • Vertical Dopingless Dual-Gate Junctionless FET for Digital and RF Analog Applications Garg A.;Singh B.;Singh Y. Silicon , Vol. 16 (2024) , pp. 2719-2728
  • Performance Evaluation of Nanosheet Junctionless FET for switching applications Garg A.;Singh B.;Singh Y. 2023 2nd International Conference on Advances in Computational Intelligence and Communication Icacic 2023 , Vol. (2023) , pp.
  • Dual-Channel Junctionless FETs for Improved Analog/RF Performance Garg A.;Singh Y.;Singh B. Silicon , Vol. 13 (2021) , pp. 1499-1507
  • Dual-Gate Junctionless FET on SOI for High Frequency Analog Applications Garg A.;Singh B.;Singh Y. Silicon , Vol. 13 (2021) , pp. 2835-2843
  • A new trench double gate junctionless FET: A device for switching and analog/RF applications Garg A.;Singh B.;Singh Y. AEU International Journal of Electronics and Communications , Vol. 118 (2020) , pp.
  • Nanoscale SiGe Double Gate MOSFET (DG-MOSFET) for Analog/RF Circuits Garg A.;Singh Y. Proceedings 2019 International Conference on Electrical Electronics and Computer Engineering Upcon 2019 , Vol. (2019) , pp.
  • Performance Optimization of Vertical Gaussian Doped SOI Junctionless FET with Substrate Bias Effects Garg A.;Singh Y.;Singh B. Proceedings 2019 Women Institute of Technology Conference on Electrical and Computer Engineering Witcon Ece 2019 , Vol. (2019) , pp. 223-226
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